EC8095 – NOTES & QP
| NOTES | CLICK HERE |
| SEMESTER QP | CLICK HERE |
EC8095 – SYLLABUS
UNIT I INTRODUCTION TO MOS TRANSISTOR
MOS Transistor, CMOS logic, Inverter, Pass Transistor, Transmission gate, Layout Design Rules, Gate Layouts, Stick Diagrams, Long-Channel I-V Charters tics, C-V Charters tics, Non ideal I-V Effects, DC Transfer characteristics, RC Delay Model, Elmore Delay, Linear Delay Model, Logical effort, Parasitic Delay, Delay in Logic Gate, Scaling.
UNIT II COMBINATIONAL MOS LOGIC CIRCUITS
Circuit Families: Static CMOS, Ratioed Circuits, Cascode Voltage Switch Logic, Dynamic Circuits, Pass Transistor Logic, Transmission Gates, Domino, Dual Rail Domino, CPL, DCVSPG, DPL, Circuit Pitfalls. Power: Dynamic Power, Static Power, Low Power Architecture.
UNIT III SEQUENTIAL CIRCUIT DESIGN
Static latches and Registers, Dynamic latches and Registers, Pulse Registers, Sense Amplifier Based Register, Pipelining, Schmitt Trigger, Monostable Sequential Circuits, Astable Sequential Circuits.
Timing Issues : Timing Classification Of Digital System, Synchronous Design.
UNIT IV DESIGN OF ARITHMETIC BUILDING BLOCKS AND SUBSYSTEM
Arithmetic Building Blocks: Data Paths, Adders, Multipliers, Shifters, ALUs, power and speed tradeoffs, Case Study: Design as a tradeoff.
Designing Memory and Array structures: Memory Architectures and Building Blocks, Memory
Core, Memory Peripheral Circuitry.
UNIT V IMPLEMENTATION STRATEGIES AND TESTING
FPGA Building Block Architectures, FPGA Interconnect Routing Procedures. Design for Testability: Ad Hoc Testing, Scan Design, BIST, IDDQ Testing, Design for Manufacturability, Boundary Scan.