EE3302 – NOTES & QP
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| SEMESTER QP | CLICK HERE |
EE3302 – SYLLABUS
UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES
Review of number systems, binary codes, error detection and correction codes (Parity and Hamming code) — Digital Logic Families -comparison of RTL, DTL, TTL, ECL and MOS families -operation, characteristics of digital logic family.
UNIT II COMBINATIONAL CIRCUITS
Combinational logic — representation of logic functions-SOP and POS forms, K-map representations — minimization using K maps — simplification and implementation of combinational logic — multiplexers and de multiplexers — code converters, adders, subtractors, Encoders and Decoders.
UNIT III SYNCHRONOUS SEQUENTIAL CIRCUITS
Sequential logic- SR, JK, D and T flip flops — level triggering and edge triggering — counters — asynchronous and synchronous type — Modulo counters — Shift registers — design of synchronous sequential circuits — Moore and Melay models- Counters, state diagram; state reduction; state assignment.
UNIT IV ASYNCHRONOUS SEQUENTIAL CIRCUITS AND PROGRAMMABILITY LOGIC DEVICES
Asynchronous sequential logic circuits-Transition tability, flow tability-race conditions, hazards &errors in digital circuits; analysis of asynchronous sequential logic circuits – Introduction to Programmability Logic Devices: PROM — PLA –PAL, CPLD-FPGA.
UNIT V VHDL
RTL Design — combinational logic — Sequential circuit — Operators — Introduction to Packages — Subprograms — Test bench. (Simulation /Tutorial Examples: adders, counters, flip flops, Multiplexers & De multiplexers).